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ADT7473
Table 64. REGISTER 0X42 ? INTERRUPT STATUS REGISTER 2 (POWER-ON DEFAULT = 0X00)
Bit No.
<0>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Mnemonic
RES
THERM
Limit Latch
OVT
FAN1
FAN2
FAN3
F4P
D1
D2
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
R/W
Read-only
Read-only
Read-only
Description
Reserved on the ADT7473
On the ADT7473 ? 1, THERM Limit Latch = 1 indicates Remote Channel 2 latch. This is a
THERM limit condition.
OVT = 1 indicates one of the THERM overtemperature limits is exceeded. This bit is cleared
on a read of the status register when the temperature drops below THERM – T HYST .
FAN1 = 1 indicates Fan 1 has dropped below minimum speed or has stalled. This bit is not
set when the PWM1 output is off.
FAN2 = 1 indicates Fan 2 has dropped below minimum speed or has stalled. This bit is not
set when the PWM2 output is off.
FAN3 = 1 indicates Fan 3 has dropped below minimum speed or has stalled. This bit is not
set when the PWM3 output is off.
F4P = 1 indicates Fan 4 has dropped below minimum speed or has stalled. This bit is not set
when the PWM3 output is off.
When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of
the GPIO.
If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit is set
when the THERM assertion time exceeds the limit programmed in the THERM timer limit
register (Reg. 0x7A).
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 65. VOLTAGE LIMIT REGISTERS (Note 1)
Register Address
0x46
0x47
0x48
0x49
R/W
R/W
R/W
R/W
R/W
V CCP Low Limit
V CCP High Limit
V CC Low Limit
V CC High Limit
Description (Note 2)
Power-On Default
0x00
0xFF
0x00
0xFF
1. Setting the Configuration Register 1 Lock bit has no effect on these registers.
2. High limits: an interrupt is generated when a value exceeds its high limit (> comparison). Low limits: an interrupt is generated when a value
is equal to or below its low limit ( ? comparison).
Table 66. TEMPERATURE LIMIT REGISTERS (Note 1)
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description (Note 2)
Remote 1 Temperature Low Limit
Remote 1 Temperature High Limit
Local Temperature Low Limit
Local Temperature High Limit
Remote 2 Temperature Low Limit
Remote 2 Temperature High Limit
Power-On Default
0x01
0xFF
0x01
0xFF
0x01
0xFF
1. Exceeding any of these temperature limits by 1 ? C causes the appropriate status bit to be set in the interrupt status register. Setting the
Configuration Register 1 Lock bit has no effect on these registers.
2. High limits: an interrupt is generated when a value exceeds its high limit (> comparison). Low limits: an interrupt is generated when a value
is equal to or below its low limit ( ? comparison).
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